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asahi kasei [AK4562] ms0031-e-00 2000/05 - 1 - features 1. resolution : 20bits 2. recording functions 2-stereo inputs mixer analog input pga monaural mixing digital hpf for dc-offset cancellation (fc=3.4hz@fs=44.1khz) 3. playback functions digital de-emphasis filter (tc=50/15us, fs=32khz, 44.1khz and 48khz) analog output pga 2 types stereo outputs (dac and analog output pga) 4. power management 5. adc characteristics input level : 1.5vpp = 0.6 x vref@vref=2.5v s/(n+d) : 82db dr, s/n : 88db 6. dac characteristics output level : 1.5vpp = 0.6 x vref@vref=2.5v s/(n+d) : 86db dr, s/n : 93db 7. 3-wire serial control, ssb i/f 8. master clock : 256fs/384fs 9. audio data format : msb first, 2s compliment adc : 20bit msb justified, i 2 s dac : 16bit lsb justified, 20bit lsb justified, 24bit lsb justified, i 2 s 10. power supply codec, pga : 2.2 ~ 3.0v (typ. 2.5v) digital i/f : 1.8 ~ 3.0v (typ. 2.5v) 11. power supply current ipga + adc : 7ma dac + opga : 5.5ma 12. ta = -20 ~ 70 c 13. package : 28pin qfn size : 5.2mm x 5.2mm height : 1mm (max) pitch : 0.5mm low power 20bit ds codec with pga AK4562
asahi kasei [AK4562] ms0031-e-00 2000/05 - 2 - n block diagram lin1 lout1 rout1 va agnd vt vd dgnd sdto lrck bclk sdti audio i/f controller adc hpf dac clock divider mclk control register i/f ssb cdti cclk (ssi) (sck) vcom rout2 opgar lout2 opgal lin2 rin1 rin2 csn pdn vref tst
asahi kasei [AK4562] ms0031-e-00 2000/05 - 3 - n ordering guide AK4562vn -20 ~ +70 c 28pin qfn (0.5mm pitch) akd4562 evaluation board for AK4562 n pin layout top view 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 9 10 11 12 13 14 16 17 18 19 20 21 rout2 lin1 rin2 lout1 rout1 opgal pdn csn cclk cdti sdto sdti bclk tst mclk lrck va vref vd dgnd vt opgar lout2 rin1 lin2 vcom agnd 15 ssb
asahi kasei [AK4562] ms0031-e-00 2000/05 - 4 - pin/function no. pin name i/o function 1 opgar i rch opga input pin 2 lout2 o lch opga output pin 3 rout2 o rch opga output pin 4 lin1 i lch #1 input pin 5 rin1 i rch #1 input pin 6 lin2 i lch #2 input pin 7 rin2 i rch #2 input pin 8 vcom - analog common voltage output pin, 0.45 x va 9 agnd - analog ground pin 10 va - analog power supply pin, +2.5v 11 vref - analog voltage reference input pin. used as a voltage reference of adc & dac. vref is connected externally to filtered va. 12 vd - digital power supply pin, +2.5v 13 dgnd - digital ground pin 14 vt - digital interface power supply pin 15 sdto o audio serial data output pin 16 sdti i audio serial data input pin 17 bclk i audio serial data clock pin 18 tst i test mode pin, fixed to l 19 mclk i master clock input pin 20 lrck i input/output channel clock pin 21 cdti i control data input pin, ssb mode: ssi 22 cclk i control clock input pin, ssb mode: sck 23 csn i chip select pin, ssb mode: h 24 pdn i reset & power down pin, l: power down & reset, h: normal operation 25 ssb i control i/f mode select pin, l: akm mode, h: ssb mode 26 lout1 o lch dac output pin 27 opgal i lch opga input pin 28 rout1 o rch dac output pin note : all digital input pins should not be left floating.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 5 - absolute maximum ratings (agnd, dgnd=0v; note 1) parameter symbol min max units power supply analog digital 1 digital 2 vd C va |dgnd C agnd| (note 2) va vd vt vda d gnd -0.3 -0.3 -0.3 - - 4.6 4.6 4.6 0.3 0.3 v v v v v input current (any pin except supplies) iin - 10 ma analog input voltage lin1-2, rin1-2, opgal, opgar, vref pins vina -0.3 va+0.3 v digital input voltage vind -0.3 vt+0.3 v ambient temperature (power applied) ta -20 70 c storage temperature tstg -65 150 c note : 1. all voltages with respect to ground. note : 2. agnd and dgnd must be same voltage. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd=0v; note 1) parameter symbol min typ max units power supply analog (va pin) digital 1 (vd pin) (note 3) digital 2 (vt pin) va vd vt 2.2 2.2 / va-0.3 1.8 2.5 2.5 2.5 3.0 va vd v v v voltage reference analog voltage reference (note 4) vref - - va v note : 1. all voltages with respect to ground. note : 3. min value is high value either 2.2v or va-0.3v. note : 4. vref and va must be same voltage. warning: akm assumes no responsibility for the usage beyond the conditions in this data sheet.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 6 - analog characteristics (ta=25 c; va, vd, vt=2.5v; fs=44.1khz; signal frequency=1khz; measurement frequency=10hz ~ 20khz; unless otherwise specified) parameter min typ max units resolution 20 bits input pga characteristics (ipga): input voltage (lin1, lin2, rin1, rin2) (note 5) 1.35 1.5 1.65 vpp input impedance 6.3 9 15.0 k w step width +28db ~ -8db -8db ~ -16db -16db ~ -32db -32db ~ -40db -40db ~ -52db 0.1 0.1 0.1 - - 0.5 1 2 2 4 1 2 4 - - db db db db db adc analog input characteristics: (note 6) s/(n+d) (-0.5dbfs input) 74 82 db d-range (eiaj) 82 88 db s/n (eiaj) 82 88 db interchannel isolation 90 100 db interchannel gain mismatch 0.2 0.5 db dac analog output characteristics: measured at lout1/rout1 (note 7) s/(n+d) 78 86 db d-range (eiaj) 87 93 db s/n (eiaj) 87 93 db interchannel isolation 90 100 db interchannel gain mismatch 0.2 0.5 db output voltage 1.35 1.5 1.65 vpp load resistance 10 k w load capacitance 20 pf output pga characteristics (opga): s/(n+d) (note 8) 82 92 db s/n (eiaj) (note 8) 89 95 db noise level at mute (eiaj) (note 9) - 108 - db input voltage (note 10) 1.5 1.65 vpp output voltage (note 10) 1.5 1.65 vpp input impedance 30 50 80 k w load resistance 10 k w load capacitance 20 pf step width +0db ~ -34db -34db ~ -64db -64db ~ -78db 0.1 0.1 - 1 2 2 2 4 - db db db note : 5. analog input voltage (full-scale voltage: ipga = 0db) scale with vref. (ipga = adc = 0.6 x vref.) note : 6. adc is input from lin1/rin1 or lin2/rin2 and it measures included in ipga. the value of ipga is set 0db. internal hpf cancels the offset of ipga and adc. note : 7. analog output voltage scale with vref. (dac = 0.6 x vref.) note : 8. input: opgal/opgar; output: lout2/rout2; opga = 0db. note : 9. noise level when reference voltage is 1.5vpp. note : 10. analog input/output voltage scale with vref. (opga = 0.6 x vref.)
asahi kasei [AK4562] ms0031-e-00 2000/05 - 7 - power supplies power supply current: va+vd+vt normal operation (pdn=h) ad+da (pm0=1, pm1=1, pm2=1, pm3=1) ad (pm0=1, pm1=1, pm2=0, pm3=0) da (pm0=0, pm1=0, pm2=1, pm3=1) power down (pdn=l) (note 11) 12.0 7.0 5.5 10 17.0 - - 100 ma ma ma ua note : 11. in case of power-down mode, all digital input pins including clocks pins (mclk, bclk and lrck) are held vt or dgnd. pdn pin is held dgnd.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 8 - filter characteristics (ta=-20 ~ 70 c; va, vd=2.2 ~ 3.0v, vt=1.8 ~ 3.0; fs=44.1khz; de-emphasis = off) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 12) 0.1db -1.0db -3.0db pb 0 20.0 21.1 17.4 khz khz khz stopband (note 12) sb 27.0 khz passband ripple pr 0.1 db stopband attenuation sa 65 db group delay (note 13) gd 17.0 1/fs group delay distortion d gd 0us adc digital filter (hpf): frequency response (note 12) -3db -0.5db -0.1db fr 3.4 10 22 hz hz hz dac digital filter: passband (note 12) 0.1db -6.0db pb 0 22.05 20.0 khz khz stopband (note 12) sb 24.1 khz passband ripple pr 0.06 db stopband attenuation sa 43 db group delay (note 13) gd 14.7 1/fs group delay distortion d gd 0us dac digital filter + analog filter frequency response 0 ~ 20.0khz fr 0.5 db note : 12. the passband and stopband frequencies scale with fs (sampling frequency). for examples, pb=0.454 x fs(@adc: -1.0db), pb=0.454 x fs(@dac: -0.1db). note : 13. the calculating delay time which occurred by digital filtering. this time is from the input of analog signal to setting the 20bit data of both channels to the output register for adc and include group delay of hpf. for dac, this time is from setting the data of both channels on input register to the output of analog signal. dc characteristics (ta=-20 ~ 70 c; va, vd=2.2 ~ 3.0v, vt=1.8 ~ 3.0v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 75 % vt - - - - 25 % vt v v high-level output voltage (iout=-400ua) low-level output voltage (iout=400ua) voh vol vt-0.4 - -- 0.4 v v input leakage current iin - - 10 ua
asahi kasei [AK4562] ms0031-e-00 2000/05 - 9 - switching characteristics (ta=-20 ~ 70 c; va, vd=2.2 ~ 3.0v, vt=1.8 ~ 3.0v; c l =20pf) parameter symbol min typ max units control clock frequency master clock (mclk) 256fs: frequency pulse width low pulse width high 384fs: frequency pulse width low pulse width high channel clock (lrck) frequency duty cycle fclk tclkl tclkh fclk tclkl tclkh fs 2.048 28 28 3.072 23 23 8 45 11.2896 16.9344 44.1 12.8 19.2 50 55 mhz ns ns mhz ns ns khz % audio interface timing bclk period bclk pulse width low pulse width high bclk to lrck lrck edge to sdto (msb) bclk to sdto sdti hold time sdti setup time tblk tblkl tblkh tblr tdlr tdss tsdh tsds 312.5 130 130 -tblkh+50 50 50 tblkl-50 80 80 ns ns ns ns ns ns ns ns control interface timing (akm) cclk period cclk pulse width low pulse width high cdata setup time cdata hold time csn h time csn to cclk - cclk - to csn - tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns control interface timing (ssb) sck period sclk pulse width low pulse width high ssi setup time ssi hold time tsck tsckl tsckh tsis tsih 250 100 100 50 50 ns ns ns ns ns reset / calibration timing pdn pulse width pdn - to sdto (note 14) tpw tpwv 150 4128 ns 1/fs note : 14. these cycles are the numbers of lrck rising from pdn pin rising.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 10 - n timing diagram mclk 1/fclk tclkh tclkl vih vil lrck 1/fs vih vil bclk tblk vih vil tblkh tblkl figure 1. clock timing vih vih lrck vil vih bclk tblr vil tdlr tdss sdto vil 50%vt tsds tsdh sdti d20 (msb) lsb figure 2. audio data input/output timing (audio i/f = no.0) csn tcss tcckl vih vil cclk vih vil cdti tcds vih vil op0 op1 tcckh tcdh op2 a0 figure 3. write command input timing (akm)
asahi kasei [AK4562] ms0031-e-00 2000/05 - 11 - csn vih vil cclk vih vil cdti vih vil d5 d6 tcsh d7 tcsw d4 figure 4. write data input timing (akm) sck vih vil ssi tsis vih vil tsih tsckl tsckh figure 5. write data input timing (ssb) pdn sdto vil tpwv tpw 50%vt figure 6. reset timing
asahi kasei [AK4562] ms0031-e-00 2000/05 - 12 - operation overview n system clock the clocks that are required to operate are mclk (256fs/384fs), lrck (fs) and bclk (32fs ~ ). the master clock (mclk) should be synchronized with lrck but the phase is free of care. the frequency of mclk can be input 256fs or 384fs. when the 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling frequency. all external clocks (mclk, bclk and lrck) should always be present whenever adc and dac are in operation. if these clocks are not provided, the AK4562 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed internally. if the external clocks are not present, the AK4562 should be in the power-down mode. n audio data i/f format using sdto, sdti, bclk and lrck pins are connected to external system. audio data format has four kinds of mode, the data format is msb-first, 2s compliment. setting by dif0-1 bit. the default value is dif0 = dif1 = 0. no. dif1 bit dif0 bit sdto (adc) sdti (dac) lrck bclk 0 0 0 20bit msb justified 20bit lsb justified lch: h, rch: l 3 40fs 1 0 1 20bit msb justified 16bit lsb justified lch: h, rch: l 3 32fs 2 1 0 20bit msb justified 24bit lsb justified lch: h, rch: l 3 48fs 31 1 i 2 s compatible i 2 s compatible lch: l, rch: h 3 40fs table 1. audio data format lrck bclk(64fs) sdto(o) 0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 19 1 18 0 19 18 8 7 6 0 19 sdti(i) 1 18 0 19 12 11 1 18 0 19 12 11 19:msb, 0:lsb lch data rch data dont care dont care 876 figure 7. audio data format (no.0) lrck bclk(64fs) sdto(o) 0 1 2 15 16 17 20 21 31 0 1 2 15 16 17 20 21 31 0 19 1 18 0 19 18 5 4 3 0 19 sdti(i) 1 15 0 12 11 1 15 0 12 11 sdto-19:msb, 0:lsb; sdti-15:msb, 0:lsb lch data rch data dont care dont care 543 figure 8. audio data format (no.1)
asahi kasei [AK4562] ms0031-e-00 2000/05 - 13 - lrck bclk(64fs) sdto(o) 0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 19 1 18 0 19 18 12 11 10 0 19 sdti(i) 1 22 0 23 12 11 1 22 0 23 12 11 sdto-19:msb, 0:lsb; sdti-23:msb, 0:lsb lch data rch data dont care dont care 12 11 10 figure 9. audio data format (no.2) lrck bclk(64fs) sdto(o) 0 1 2 3 19 20 21 22 0 1 2 3 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 19 18 0 19 18 1 0 1 0 18 19 18 19 19:msb, 0:lsb lch data rch data dont care dont care 1 10 figure 10. audio data format (no.3) n digital high pass filter the AK4562 has a digital high pass filter (hpf) to cancel dc-offset in adc and ipga. the cut-off frequency of the hpf is 3.4hz at fs=44.1khz. it also scales with the sampling frequency (fs). n system reset & offset calibration the AK4562 should be reset once by bringing pdn pin l after power-up. the control register values are initialized by pdn l. offset calibration starts by pdn pin l to h. it takes 4128/fs to offset calibration cycle. during offset calibration, the adc digital data outputs of both channels are forced to a 2s compliment 0. output data of settles data equivalent for analog input signal after offset calibration. this cycle is not for dac. ipga and opga are set mute during offset calibration and after offset calibration. as a normal offset calibration may not be executed, nothing write at address 01h during offset calibration. when offset calibration is executed once, the calibration memory is held even if each block is powered down (pm0 = 0 or pm3 = 0) by power management bits.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 14 - the clocks may be stopped. 4128/fs pdn pin power supply adc internal state control register w rite to register dac internal state external clocks ain sdto sdti aout1 pd pdn pin may be l at power-up. cal normal gd gd gd (1) 0data (3) 0data pd (2) pm normal (1) idle noise normal pm normal 0 data gd (1) gd (1) (5) (5) init-2 normal inhibit-1 inhibit-2 normal (6) 4128/fs init-1 gd (1) (6) (4) figure 11. power up / power down timing example pd: power-down state. adc is output 0, analog output of dac and opga goes floating. pm: power-down state by power management bit. adc is output 0, analog output of dac goes floating. cal: during offset calibration cycle. ipga and opga are set mute state. init-1: initialize cycle of adc. offset calibration is not executed. init-2: initializing all control registers. inhibit-1: inhibits writing to all control registers. inhibit-2: enable writing to control registers except address 01h. note: see register definitions about the condition of each register. (1). digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). output signal gradually comes to settle to input signal during a group delay. (2). if the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of a internal adc. (3). adc output is 0 at power down. (4). this figure shows that mute of ipga is canceled during offset calibration. if mute of ipga is canceled, sdto outputs idle noise. (5). click noise occurs at the - of pdn signal. please mute the analog output external if the click noise influences system application. (6). when the external clocks (mclk, bclk and lrck) are stopped, the AK4562 should be in the power down (pdn pin = l or pm2-1 bit = 0) mode.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 15 - n timing of control register akm mode akm mode is the data in i/f with 3-wire serial control, these data are included by op-code (3bit), address (lsb-first, 5bit) and control data (lsb-first, 8bit). a side of transmitted data is output to each bit by of cclk, a side of receiving data is input by - of cclk. writing of data becomes effective by - of csn. csn should be held to h at no access. address except 00h ~ 04h inhibits control of writing. and cclk always need 16 edges of - during csn = l. csn cclk 01 2 345 67891011 12 13 14 15 cdti op0 op1 a2 a1 a3 a4 a0 d0 d1 d2 d3 d4 d5 d6 d7 op2 op0-op2: op code (fixed to **1: write) a0-a4: register address d0-d7: control data 1 * * figure 12. control data timing (akm) ssb mode ssb mode is the data in i/f with 2-wire serial interface, these data are included by information bit (3bit) and data bit (lsb-first, 8bit). serial clock (sck) is burst-transmitted, not continuous receiving data. transmitter outputs each bit by - of sck, receiver latches the bit when transmitting the data is input by of sck. writing of data and command becomes effective by next - of sck after taking in the last data bit (d7). address except 00h ~ 04h inhibits control of writing. command write sck 01 2 345 678910 ssi 1 st r/w d0 d1 d2 d3 d4 d5 d6 d7 d/c st: start bit (1: start) r/w: read/write bit (fixed to 1: write) d/c: data/command bit (0: data, 1: command) d0-d7: address or control data data write st wr d0 d1 d2 d3 d4 d5 d6 d7 c 1 1 d0-d3: device code, d4-d7: instruction code st wr d0 d1 d2 d3 d4 d5 d6 d7 d 1 1 d0-d7: address or control data 0 figure 13. control data timing (ssb)
asahi kasei [AK4562] ms0031-e-00 2000/05 - 16 - n register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h input select 0 0 0 0 rin2 rin1 lin2 lin1 01h mode control 1 0 0 0 0 pm3 pm2 pm1 pm0 02h mode control 2 mono1 mono0 ztm1 ztm0 dem1 dem0 dif1 dif0 03h input analog pga control zeip ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 04h output analog pga control zeop opga6 opga5 opga4 opga3 opga2 opga1 opga0 all registers are reset at pdn = l, then inhibits writing to all registers. n register definition input select addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h input select 0 0 0 0 rin2 rin1 lin2 lin1 reset 0 0000101 lin2-1: select on/off of lch input. (0: off, 1: on) rin2-1: select on/off of rch input. (0: off, 1: on) mode control 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h mode control 1 0 0 0 0 pm3 pm2 pm1 pm0 reset 0 0001111 pm3-0: power management (0: power down, 1: power up) pm0:power control of imix and ipga pm1:power control of adc pm2:power control of dac pm3:power control of opga pm3-0 can be partly powered-down by on/off of pm3-0. when pdn pin goes l, all circuit in the AK4562 can be powered-down in no relation to pm3-0. when pm3-0 goes all 0, all circuit in the AK4562 can be also powered-down. however, the contents of control registers are held. in case of pm1 = 1 or pm2 = 1, mclk is not stopped. in case of pm0 = 1 or pm3 = 1, the powered-up circuit does not need mclk. however, zero crossing detection can not operate in this case.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 17 - organizatio n of power ma nagement bit imix ipga adc dac opga pm3 pm2 pm1 pm0 1) all circuit p ower-up 2) rec mo nitor 3) no rec mo nitor 4) play 5) all circuit power-down pm0=1 pm1=1 pm2=1 pm3=1 imix ipga adc dac opga pm3 pm2 pm1 pm0 pm0=1 pm1=1 pm2=1 pm3=1 pm0=1 pm1=1 pm2=0 pm3=0 pm0=0 pm1=0 pm2=1 pm3=1 pm0=0 pm1=0 pm2=0 pm3=0 imix ipga adc dac opga pm3 pm2 pm1 pm0 imix ipga adc pm1 pm0 dac opga pm3 pm2 figure 14. power management
asahi kasei [AK4562] ms0031-e-00 2000/05 - 18 - mode control 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h mode control 2 mono1 mono0 ztm1 ztm0 dem1 dem0 dif1 dif0 reset 0 0110100 mono1-0: monaural mixing 00: stereo (reset) 01: (l+r)/2 10: ll 11: rr ztm1-0: setting of zero crossing timeout for ipga and opga 00: 256/fs 01: 512/fs 10: 1024/fs 11: 2048/fs (reset) dem1-0: select frequency of de-emphasis 00: 44.1khz on 01: off (reset) 10: 48khz on 11: 32khz on dif1-0: select digital interface format no. dif1 bit dif0 bit sdto(adc) sdti(dac) lrck bclk 0 0 0 20bit msb justified 20bit lsb justified lch: h, rch: l 3 40fs reset 1 0 1 20bit msb justified 16bit lsb justified lch: h, rch: l 3 32fs 2 1 0 20bit msb justified 24bit lsb justified lch: h, rch: l 3 48fs 31 1 i 2 s compatible i 2 s compatible lch: l, rch: h 3 40fs table 2. audio data format
asahi kasei [AK4562] ms0031-e-00 2000/05 - 19 - input analog pga control addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h input analog pga control zeip ipga6 ipga5 ipga4 ipga3 ipga2 ipga1 ipga0 reset 0 00h (mute) zeip: select ipga zero crossing operation (0: disable, 1: enable) writing to ipga value at zeip = 1, ipga value of l/r channels changes by zero crossing detection or timeout independently. in the timeout cycle, it is possible to set in ztm1-0 bit. when ztm1-0 is 11, timeout cycle is 2048/fs = 46.4ms (@fs=44.khz). when zeip is 0, ipga changes immediately. ipga6-0: input analog pga. 97 levels. 00h=mute. on/off of zero crossing detection can be controlled by zeip bit. data gain (db) step level 60h +28.0 5fh +27.5 5eh +27.0 28h +0.0 27h -0.5 19h -7.5 18h -8.0 0.5db 73 17h -9.0 16h -10.0 11h -15.0 10h -16.0 1db 8 0fh -18.0 0eh -20.0 05h -38.0 04h -40.0 2db 12 03h -44.0 02h -48.0 01h -52.0 4db 3 00h mute 1 table 3. input gain setting
asahi kasei [AK4562] ms0031-e-00 2000/05 - 20 - about zero crossing operation comparator for zero crossing detection in the AK4562 has offset. therefore, it is a possible that ipga (opga) value is changed by zero crossing timeout as zero crossing detection does not occur by a little offset of comparator. for example, when lch and rch are in the state of ipga (opga) = 30h, both channels are set to ipga (opga) = 31h. and then the only lch completed zero crossing, rch is waiting for zero crossing detection, zero crossing counter is reset when ipga (opga) is newly written 32h, zero crossing operation starts toward ipga (opga) = 32h in state lch = 31h, rch = 30h. internal ipga (opga) value in the AK4562 has the registers of l/r channels independently, according to change ipga (opga) value independently, ipga (opga) value of l/r channels may become a difference in level. therefore, if ipga (opga) is written before zero crossing detection on zero crossing timeout, ipga (opga) is keeping the same value. when ipga (opga) is finished by normal zero crossing timeout on ipga (opga) value of l/r channels does not give a difference in level, the change of ipga (opga) should be written after zero crossing timeout cycle and over. internal zero crossing operation completion flag lch internal ipga (opga) rch internal ipga (opga) ipga register (opga) zero crossing 30h 31h 32h 30h 30h 32h 31h 30h 32h wr[ipga(opga)=31h] reset zero crossing timer wr[ipga(opga)=32h] reset zero crossing timer figure 15. about zero crossing operation
asahi kasei [AK4562] ms0031-e-00 2000/05 - 21 - output analog pga control addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h output analog pga control zeop opga6 opga5 opga4 opga3 opga2 opga1 opga0 reset 0 00h (mute) zeop: select opga zero crossing operation (0: disable, 1: enable) writing to opga value at zeop = 1, opga value of l/r channels changes by zero crossing detection or timeout independently. timeout cycle can be set by ztm1-0 bit. when ztm1-0 is 11, timeout cycle is 2048/fs = 46.4ms (@fs=44.khz). when zeop is 0, opga changes immediately. opga6-0: output analog pga. 58 levels. 00h=mute. on/off of zero crossing detection can be controlled by zeop bit. please do not use 3ah ~ 7fh. data (d6-0) hex code opga (db) step level 011 1001 39h +0 011 1000 38h -1 011 0111 37h -2 001 1000 18h -33 001 0111 17h -34 1db 35 001 0110 16h -36 001 0101 15h -38 000 0011 03h -74 000 0010 02h -76 000 0001 01h -78 2db 22 000 0000 00h mute 1 table 4. output gain setting
asahi kasei [AK4562] ms0031-e-00 2000/05 - 22 - n detail of functions (1) input analog pga with zero crossing detection zero crossing is detected on l/r channels independently. if zero crossing is not detected, ipga value changes by timeout. timeout cycle can be set by ztm1-0 bit. for example, when ztm1-0 is 11, timeout cycle is 2048/fs = 46.4ms (@fs=44.khz). zero crossing detection function can be controlled by on/off of zeip bit. if zeip is off, gain level changes immediately by writing ipga value. offset calibration starts by pdn pin l to h. ipga is set mute during offset calibration and after offset calibration. (2) monaural mixing adc hpf lch rch adc hpf + x 0.5 lch rch selector selector sw1 sw2 figure 16. monaural mixing mode sw1 sw2 mono1 mono0 stereo recording lch rch 0 0 monaural recording stereo input (l+r)/2 (l+r)/2 0 1 monaural recording lch input only lch lch 1 0 monaural recording rch input only rch rch 1 1 table 5. monaural mode setting (3) de-emphasis include digital de-emphasis filter circuit with tc=50/15us.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 23 - (4) output analog pga with zero crossing detection zero crossing is detected on l/r channels independently. if zero crossing is not detected, opga value changes by timeout. timeout cycle can be set by ztm1-0 bit. for example, when ztm1-0 is 11, timeout cycle is 2048/fs = 46.4ms (@fs=44.khz). zero crossing detection function can be controlled by on/off of zeop bit. if zeop is off, gain level changes immediately by writing opga value. offset calibration starts by pdn pin l to h. opga is set mute during offset calibration and after offset calibration. usually, to remove the offset of dac, it needs a capacitor (ca) between lout1/rout1 and opgal/opgar. the cut off frequency is decided by capacity of ca and input impedance (typ. 50k w ) of opga. lout1/rout1 ca cr 50k opga lout2/rout2 figure 17. example of connection between lout1/rout1 and lout2/rout2 (5) power management power down and analog through mode in each block are controlled by 4bit. (6) ssb i/f summary 2-wire bit rate: max. 4mbps AK4562 has the device code (max. 4bits, AK4562 is fixed to 05h.), enable to connect bus to the maximum 16 devices. each device accepts data after recognizing own device code. data transmitting to continuity address is enabled by the appointed address at once as there is the auto- increment/auto-decrement functions. the counter with 14 bit shift register starts from a start bit, if there is a 14th carrier, the counter is reset by recognizing the first 1 as the start bit. sck 01 2 34 5 678910 ssi str/w d0d1d2d3d4d5d6d7 d/c s t: s ta rt b it (1 : s ta rt) r/w : read/w rite bit (fi xed to 1: w rite) d/c: data/com m and bit (0: data, 1: command) d0-d7: addr ess or control data figure 18. ssb timing
asahi kasei [AK4562] ms0031-e-00 2000/05 - 24 - write command when d/c bit is 1, 8 bit data after information bits indicates a command. sck ssi 01 2 34 5 678910 st wr d0 d1 d2 d3 d4 d5 d6 d7 c d0-d3: device code d0-d7: instruction code 11 12 13 0 1 2 st wr d internal w rite tim ing figure 19. write command timing device code d0-3 bits are the device code, the bus can be connected to maximum 16 devices, however, and the device code is fixed to 05h in the AK4562. instruction code the following instruction is set by d4-d7 bits. instruction code d4 d5 d6 d7 command function 0 0 0 0 reset only the contents of control register are reset. 1 0 0 0 adrsl when the next data is data write, the address is sent. if not so, this command is invalidated. 0 1 0 0 nop invalidity 1 1 0 0 ainc auto increment mode of address holds this state until sending the next adec and ahold. 0 0 1 0 adec auto decrement mode of address holds this state until sending the next ainc and ahold. 1 0 1 0 ahold fixed mode of address holds this state until sending the next ainc and adec. 0110 - - - - - 0111 nop invalidity 1 1 1 1 reset only the contents of control register are reset. table 6. ssb instruction ssb i/f becomes disable by pdn = l, it is set to address = 00h, ahold mode. therefore, after exiting pdn = l at power-on, ssb i/f is enabled by writing command (including nop) of a appointed device code and accepts data write ever since. data write when d/c bit is 0, 8 bit data after the information bits indicates data. if adrsl command is sent just before the data is written as the address. the control data is sent in the other case. sck ssi 01 2 345 678910 st wr d0 d1 d2 d3 d4 d5 d6 d7 d d0-d7: address or control data 11 12 13 0 1 2 st wr d internal write timing figure 20. data write timing
asahi kasei [AK4562] ms0031-e-00 2000/05 - 25 - example for access of command and data [write operation] specific device + ainc specific device + adrsl write address data write data write data write data : command write/auto address inc : command write/write address : data write : data write (adrsl) : data write (adrsl+1) : data write (adrsl+2) until coming the command of the next specific device after coming the command except specific device, ssb i/f becomes disable and writing address and writing of data are not complete done. it becomes enable at coming a command of specific device and keeps the state until coming the command except the next specific device. when address auto-increment mode or address auto-decrement mode is set, the internal address is updated after completing the operation of writing the data. adrsl in 00h ~ 04h is capable to use, but writing should not be done at setting the address except that.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 26 - system design figure 21 shows the system connection diagram. an evaluation board [akd4562] is available which demonstrates application circuit, optimum layout, power supply arrangements and measurement results. AK4562 7 6 5 4 3 2 1 28 27 26 25 24 23 22 8 1011121314 15 16 17 18 19 20 21 opgar lout2 lin1 lin2 rin2 rin1 ssb opgal rout1 lout1 pdn csn cclk cdti lrck sdto sdti bclk tst mclk vcom agnd va vref dgnd vd vt audio controller micro controller 2.2u + 0.1u 0.1u + 10u + 10u 0.1u 0.1u + 10u 2.2v ~ 3.0v analog supply 10 ohm 1.8v ~ 3.0v digital supply rout2 9 agnd system digital gnd figure 21. system connection diagram example notes: - when aout drives some capacitive load, some resistor should be added in series between aout and capacitive load. - tst pin always fixes to l. - agnd and dgnd pins connect to agnd.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 27 - 1. grounding and power supply decoupling the AK4562 requires careful attention to power supply and grounding arrangements. va and vd are usually supplied from analog supply in system. alternatively if va and vd are supplied separately, the power up sequence is not critical. vt is a power supply pin to interface with the external ics and is supplied from digital supply in system. agnd and dgnd of the AK4562 should be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4562 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference the differential voltage between vref and agnd sets the analog input/output range. vref pin is normally connected to va with a 0.1uf ceramic capacitor. vcom is a signal ground of this chip. an electrolytic capacitor 2.2uf parallel with a 0.1uf ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the vref and vcom pins in order to avoid unwanted coupling into the AK4562. 3. analog inputs the analog inputs are single-ended and the input resistance 9k w (typ). the input signal range scales with the vref voltage and nominally 0.6 x vref vpp (typ) centered in the internal common voltage (typ. 0.45 x va). usually, the input signal cuts dc with a capacitor. the cut-off frequency is fc=(1/2 p rc). the AK4562 can accept input voltages from agnd to va. the adc output data format is 2s complement. the output code is 7ffffh(@20bit) for input above a positive full scale and 80000h(@20bit) for input below a negative fill scale. the ideal code is 00000h(@20bit) with no input signal. the dc offset including adc own dc offset removed by the internal hpf (fc=3.4hz). 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage (typ 0.45 x va). the input signal range scales with the supply voltage and nominally 0.6 x vrefh vpp (typ). the dac input data format is 2s complement. the output voltage is a positive full scale for 7ffffh(@20bit) and a negative full scale for 80000h(@20bit). the ideal output is vcom voltage for 00000h(@20bit). if the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the attenuation by external filter is required. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have vcom and dc offsets of a few mv.
asahi kasei [AK4562] ms0031-e-00 2000/05 - 28 - package 28pin qfn (unit: mm) 0.25 0.10 5.0 0.10 5.2 0.20 5.0 0.10 0.2 + 0.10 - 0.20 5.2 0.20 0.50 0.22 0.05 28 22 1 8 21 0.05 m 21 15 14 8 7 1 22 45 45 0.21 0.05 0.02 + 0.03 - 0.02 0.78 + 0.17 - 0.28 0.80 + 0.20 - 0.00 0.05 7 14 15 4 - c0.6 0.60 0.10 28 note : the black parts of back package should be open. n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [AK4562] ms0031-e-00 2000/05 - 29 - marking 1 4562 xxxx xxxx : date code identifier important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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